Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

Md. Saud Al Faisal, Md. Rokib Hasan, Marwan Hossain and Mohammad Saiful Islam

Published in Volume 2 - Number 2, March 2017


Subject Area : VLSI

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Md. Saud Al Faisal, Md. Rokib Hasan (2017). Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs. Circulation in Computer Science, 2, 2 (March 2017), 15-19.

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GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

Keywords: GaN, DG-MOSFETs, SILVACO, NEGF, drain-induced barrier lowering (DIBL), gate underlap, sub threshold slope (SS)


  1. S.J. Pearson, J.C. Zolpeer, R.J. Shul, F. Ren, J. Appl. Phys. 86 (1998) 1–78.
  2. S.P. Kumar, A. Agrawal, R. Chaujar, S. Kabra, M. Gupta, R.S. Gupta, Microelectron. J. 38 (2007) 1013–1020.
  3. T. Palacios, A. Chakraborty, S. Heikman, S. Keller, S.P. Denbaars, U.K. Mishra, IEEE Electron. Dev. Lett. 27 (2006) 13–15.
  4. Y. Awano, M. Kosugi, K. Kosemura, T. Mimura, M. Abe, IEEE Trans. Electron. Dev. 36 (1989) 2260–2266.
  5. Y. Awano, M. Kosugi, T. Mimura, M. Abe, “Performance of a quarter micrometer gate ballistic electron HEMT”, IEEE Electron. Dev. Lett. 8 (1987) 451–453.
  6. D.K. Ferry, L.A. Akers, E.W. Greeneich, “Ultra Large Scale Integrated Microelectronics,” Prentice-Hall, Englewood Cliffs, NJ, 1988
  7. A. Bansal, B. C. Paul, and K. Roy, IEEE Trans. Electron. Dev. 52, 256 (2005).
  8. Z. Ren, R. Venugopal, S. Datta, M. Lundstrom, D. Jovanovic, J. Fossum, IEDM Tech. Dig. (2000) 715.
  9. M. Balaguer, B. Iñíguez, and J. B. Roldán, “An analytical compacmodel for Schottky-barrier double gate MOSFETs,”Solid-State Electron., vol. 64, no. 1, pp. 78–84, 2011.
  10. T. Sekigawa, Y. Hayashi, Solid-State Electron. 27 (1984) 827.
  11. Kranti, T., M. Chung, and J.-P. Raskin, “Analysis of static and dynamic performance of short channel double gate SOI MOSFETs for improved cut-off frequency,” Jpn. J. Appl. Phys. , vol. 44, no. 4B, 2005, pp. 2340- 2346.
  12. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S.P. Wong, “Device scaling limits of Si MOSFETs and their application dependencies,”Proc. IEEE, vol. 89, Mar. 2001, pp. 259–288.
  13. Veera Boopathy. E, Raghul. G, Karthick. K, “Low power and high performance MOSFET”, IEEE International Conference on VLSI-SATA, 2015.
  14. D. Kahng and M. M. Atalla, “The IRE Solid State Device Research Conference”, Carnegie Institute of Technology, Pittsburgh, PA June 1960.
  15. KrishnaC. Saraswat, “How far can we push Si CMOS and what are the alternatives for future VLSI," IEEE Device Research Conf., Santa Barbara, June 2014.
  16. R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A.Majumdar, M. Metz, and M. Radosavljevic, “Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications”, IEEE Transactions on Nanotechnology, vol. 4, pp. 153-158, 2005.
  17. Serge Oktyabrsky, Peide D. Ye.,"Fundamentals of III-V Semiconductor MOSFETs", 1st ed., Springer New York, Dordrecht Heidelberg, London: Springer, 2010
  18. E. Kohn and F. Medjdoub, "InA IN - A New Barrier Material for GaNBased HEMTs," in International Workshop on Physics of Semiconductor Devices, 2007. JWPSD 2007., 2007, vol. 6, pp. 311-316.
  19. A. U. Manual. Device simulation software, In Silvaco Int., Santa Clara, CA, 2008.
  20. Wei Cao, Jiahao Kang, Deblina Sarkar, Wei Liu, Kaustav Banerjee, “2D semiconductor Fets-projections and design for sub-10 nm VSLI”,IEEE Trans. On Elec. Dev. Vol. 62, NO. 11, November 2015.
  21. Ma jumdar K, Majhi P, Bhat N, et al., “A scalable, high performance, low leakage hybrid n-channel FET.”, IEEE Trans Nanotechnol, 2010, 9(3): 342.
  22. Chau R, Datta S, Majumdar A., “Opportunities and challenges of III–V nanoelectronics for future high-speed, low-power logic applications”, Compound Semiconductor Integrated Circuit Symposium, 2005: 1.
  23. S. M. Sze, Physics of Semiconductor Devices. New York, NY, USA: Wiley, 1981.

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